1. Field
The embodiments discussed herein relates to a semiconductor memory including a voltage supply circuit.
2. Description of Related Art
In a pMOS transistor in which a high voltage is applied to a gate, a gated induced drain leakage (GIDL) current may occur. The GIDL current flows from a substrate of the transistor to a drain or a source, depending on the gate voltage. The GIDL current may occur in a transistor in which a difference between the gate voltage and a drain voltage or source voltage is large. In an nMOS transistor too, when the difference between the gate voltage and the drain voltage or source voltage is large, the GIDL current may flow from the drain or source to the substrate.
Related art is disclosed in Japanese Laid-open Patent Publication No. 2003-109381, Japanese Laid-open Patent Publication No. 2005-158223, Japanese Laid-open Patent Publication No. 2008-135099, and the like.